1. Field of the Invention
This invention relates generally to an industrial processing system, and, more particularly, to determining the health of a desired node in a multi-level semiconductor fabrication processing system.
2. Description of the Related Art
There is a constant drive within the semiconductor industry to increase the quality, reliability, and throughput of integrated circuit devices, e.g., microprocessors, memory devices, and the like. This drive is fueled by consumer demands for higher quality computers and electronic devices that operate more reliably. These demands have resulted in continual improvements in the manufacture of semiconductor devices, e.g., transistors, as well as in the manufacture of integrated circuit devices incorporating such transistors. Additionally, reducing the defects in the manufacture of the components of a typical transistor also lowers the overall cost per transistor as well as the cost of integrated circuit devices incorporating such transistors.
During the fabrication process, various events may take place that affect the performance of the devices being fabricated. That is, variations in the fabrication process steps may result in device performance variations. Factors, such as feature critical dimensions, doping levels, contact resistance, particle contamination, etc., all may potentially affect the end performance of the device. Various tools in the processing line are controlled, in accordance with performance models, to reduce processing variation. Commonly controlled tools include photolithography steppers, polishing tools, etching tools, and deposition tools. Pre-processing and/or post-processing metrology data is supplied to process controllers for the tools. Operating recipe parameters, such as processing time, are calculated by the process controllers based on the performance model and the metrology information to attempt to achieve post-processing results as close to a target value as possible. Reducing variation in this manner leads to increased throughput, reduced cost, higher device performance, etc., all of which equate to increased profitability.
Semiconductor manufacturing processes, which have become more reliable and robust over the past few years, may include a plurality of processing tools that cooperate with each other to process semiconductor devices, such as microprocessors, memory devices, ASICs, etc. To verify that the processing tools are operating within acceptable parameters, it has become increasingly desirable to monitor the operating conditions of such processing tools.
Today's semiconductor manufacturing processes may include an intricate network of multiple processing tools for manufacturing semiconductor devices. In such an arrangement, while the processing tools may cooperatively work to process wafers, the fault detection analysis is typically performed on a tool-by-tool basis. That is, each processing tool generally has its own associated fault detection system for identifying faults with that particular processing tool 30. While discrete, independent fault detection systems are useful in evaluating the performance of individual processing tools, such fault detection systems provide a rather limited perspective on the overall performance of the manufacturing system. Further, the discrete, independent fault detection systems can be inflexible from the standpoint of providing varying perspectives of the performance of selected groups of processing tools, other equipment, or processes in the manufacturing system.
The present invention is directed to overcoming, or at least reducing the effects of, one or more of the problems set forth above.